Nvidia is Looking for Senior Build and Release Methodology Engineer at Bengaluru Full Time

We are looking for a Senior Engineer for our Build and Release Methodology Group catering to our pioneering SOCs.

As the SOC development becomes more complex requiring packing of more and more IPs and the need for doing more SOCs increase, we need to have a scalable infrastructure to be able to complete SOC development in fastest as well as most efficient way possible. This requires an SOC Build and IP Release infrastructure that caters to and keeps up with these ever-increasing complexities. In this position, you will work first-hand on architecting and developing this methodology. If you have real passion for methodologies and automation solutions, you will fit in great!

What you’ll be doing:

• Define and develop system-level methodologies and tools to build SOCs in an efficient and scalable manner.

• Architect and implement core build flows so as to optimize build and make it simpler and efficient.

• Improve build, release, and integration tools and procedures.

• Identify and develop Checks to enforce the best practices for the Build and Release guidelines.

• Develop solutions to enable abstraction and compartmentalization for customer IPs.

• Identify difficulties and inefficiencies in the SOC implementation process and propose ideas to solve them.

• Support IP teams with Build and Release related issues.

What we need to see:

• BS or MS in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent experience.

• At least 5 years of industry experience as Build and Release Engineer, Build Automation, IP integration and related areas.

• Strong coding skills in Perl, Python, Makefile, Shell script, or other industry-standard scripting languages.

• Excellent analytical and problem-solving skills.

• Excellent interpersonal skills to work with multi-functional teams and collaborate with team members across sites and cultures to build consensus.

• Background in RTL (Verilog), Verification (UVM, System Verilog) and C/C++ is a plus – Not must.

• Experience in synthesis and physical design is a plus – Not must.

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