Job Description
Defines the physical dimensions of the IP or SoC with consideration for overall product costs such as die size optimization, die per reticle/good die per wafer maximization, and right technology selection as it pertains to metal layers and reuse strategy across different SKUs in a product family. Establishes the integration plans for disaggregated die with optimization for package and board constraints. Performs integration of all dies in a package and completes the relevant checks before tapeout. Creates and physical database for the IP or SoC. Collaborates with architects to optimize the placement of IPs for latency as well as die area/aspect ratio. Creates specifications and collaterals for the IP blocks to execute the floorplan and automatic place and route (APR) at subsequent hierarchies. Collaborates with the clock design and logic design teams to deliver the physical block level floorplans for APR. Collaborates with the power delivery team on tradeoffs for metal allocation for signal and power.
Floorplan Engineer
Responsibilities include but not limited to:
Tops-down floorplanning of an SOC in collaboration based on IP, Package, Bump and technology constraints. Estimate of Die area
Collaboration with IP and Package owners to finalize IP Placement
Definition of Bump-map in collaboration with IP Owners and delivering Validated Die file to Packaging and other stakeholders.
Influencing Physical Partition of the Sub-Blocks, Shape and Pin Planning, Power Grid Planning and channel planning and delivering Tops-down constraints to partition owners for place and route
Definition Chip integration contour including PDK, Tools, IP and Bump versions.
Driving for Layout Verification Convergence for DRC, LVS, Density and Power Delivery
Performing RDL / Top Level routing routing and MIM insertion analysis
Qualifications
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Master of Science degree in Electrical/Computer Engineering with 10+ yrs of relevant experience, OR Bachelor of Science degree in Electrical/Computer Engineering with 12+ yrs of relevant experience
Experienced Floorplanning at Chip level/Subsystem Level at least for 4 SOCs experience of and minimum 2 SOCs as floorplan owner
Must have dealt with SOCs in High performance computing space preferable Datacenter/AI dealing with complex problem like SOC fabric floorplanning
Must have experience on 5nm or below Industry Process
Must be experienced in SNPS/Cadence floorplanning tools
Scripting Skills in Python, Perl and TCL needed.
Must be a strong communicator, excellent in verbal/written communication.
Inside this Business Group
The focus of Accelerated Computing Systems and Graphics (AXG) is to accelerate our execution in strategic growth areas of high-performance computing and graphics. AXG is chartered with delivering high performance computing and graphics solutions (IP, Software, Systems), for both integrated and discrete segments across client, enterprise and data center. Our mission is to make zeta-scale computing accessible to every human on the planet by the end of this decade and to entertain, educate and connect billions of people with buttery smooth visual experiences.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will require an on-site presence.
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