Job Description
We are looking forward to candidates with:
Strong knowledge of DFT architectures and methodologies which includes Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc
and proven knowledge of Verilog and System Verilog, RTL design and micro-architecture skills. Strong knowledge of SoC tools/methodology
( VCS, Synthesis, Spyglass, Tessent Industry standard ATPG/MBIST tools design compiler etc. and also DFT design on Physical design highly desirable).
In addition, this position requires interaction and fulfilling the requirements of Intels post-silicon/ATE teams, Silicon Debug and understanding HVM (High Volume Manufacturing) requirements. Strong debug skills and demonstrated experiences in Perl and TCL scripting are a must.
The candidate is expected to be familiar with DFT concepts in the context of multi-die package approach.
Qualifications
Qualifications:
Experience : Should have 7+ years of experience in relevant field
Bachelor Degree in Electrical and Electronics Engineering or Master Degree in Electrical and Electronics Engineering or Computer Engineering
Strong Communications skills and the ability to effectively work with cross functional teams.
Inside this Business Group
Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC’s and critical IP’s sustain Intels Xeon and 5G networking roadmap.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (https://jobs.intel.com/en/benefits)
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
Job Description Responsibilities of candidates include: • Cleaning the Office • Serve Tea / Coffee. More about this Helper job...
Apply For This JobThe Sharanalaya Montessori School in Chennai is evolving towards becoming a centre that fosters curiosity & celebrates excellence from all...
Apply For This JobJob Details Responsibilities of candidates include: • Typing documents/ material, including reports, correspondence and policies etc • Checking documents for...
Apply For This JobJob Description Planning /Budgeting Head officeQualification:BE/B.Tech in Civil Engineering or PG in Construction Management (NICMAR/SP JAIN)Experience:5-7 yrs. Preparation of project...
Apply For This JobJob Details Job Description *PLEASE READ THE WHOLE POST THOROUGHLY 👇* Hi, you showed interest for the post of *Bajaj...
Apply For This Job