Job Description
Performs physical design implementation of custom Testchip designs (including graphics, compute, display, and media) from RTL to GDS to create a design database that is ready for anufacturing. Conducts all aspects of the Testchip physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future Testchip microarchitectures closely collaborating with logic, circuit, architecture, and design automation teams. ? Possesses Testchip-specific expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, structured placement, routing, synthesis, and DFT. ? Optimizes Testchip design to improve product-level parameters such as power, frequency, and area. ? Participates in the development and improvement of physical design methodologies and flow automation.
Qualifications
Qualifications You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: Candidate must have a Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 12+ years of experience – OR – Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of experience with: Synopsys or Cadence design (RTL to GDS) tools. Synopsys-Primetime. ICV or Calibre DRC/LVS Layout cleanup Preferred Qualifications: Experience with STA at both partition and SOC level Strong analytical ability, problem solving and communication skills Ability to work independently and at various levels of abstraction Experience in Perl, TCL/Tk programming. Experience with TFM (Tools, Flows, Methodology) Development
Inside this Business Group
IP Engineering Group’s (IPG) vision Build IPs that power Intel’s leadership products and power our customer’s silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel’s silicon design process. IPG’s guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.
Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel’s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at https://jobs.intel.com/ and not fall prey to unscrupulous elements.
Working Model
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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